| ID | 34080 |
| フルテキストURL | |
| 著者 |
Michinishi, Hiroyuki
Okayama University of Science
Okamoto, Takuji
Okayama University of Science
Kobayashi, Toshifumi
Mitsubishi Electric Company Limited
Hondo, Tsutomu
Sharp Takaya Electronics Industry Company Limited
|
| 抄録 | In this paper, we propose a new I/sub DDQ/ test method for detecting floating gate defects in CMOS ICs. In the method, an unusual increase of the supply current, caused by defects, is promoted by superposing an AC component on the DC power supply. The feasibility of the test is examined by some experiments on four DUTs with an intentionally caused defect. The results showed that our method could detect clearly all the defects, one of which may be detected by neither any functional logic test nor any conventional I/sub DDQ/ test. |
| キーワード | CMOS logic circuits
electric current measurement
integrated circuit testing
logic testing
|
| 備考 | Digital Object Identifier: 10.1109/ATS.2002.1181747
Published with permission from the copyright holder. This is the institute's copy, as published in Test Symposium, 2002. (ATS '02). Proceedings of the 11th Asian, 18-20 Nov. 2002, Pages 417-422. Publisher URL:http://dx.doi.org/10.1109/ATS.2002.1181747 Copyright © 2002 IEEE. All rights reserved. |
| 発行日 | 2002-11
|
| 出版物タイトル |
Test Symposium
|
| 開始ページ | 417
|
| 終了ページ | 422
|
| 資料タイプ |
学術雑誌論文
|
| 言語 |
英語
|
| 査読 |
有り
|
| DOI | |
| Submission Path | electrical_engineering/49
|
