Programmable Clock Distribution Using Switching Matrices for Field Programmable Gate Arrays

Every digital systems using very large scale integration require clock distributions, for which a dedicated clock tree or a mesh clock is frequently used. Field programmable gate arrays have numerous general-purpose programmable wires based on switching matrices to connect the outputs and inputs of look-up tables and input–output ports. However, field programmable gate arrays never use numerous general-purpose programmable wires for their clock distributions to satisfy the clock skew margin similarly to very large scale integrations. Field programmable gate arrays also use dedicated clock trees, although their programmability is not high. Currently, field programmable gate arrays can support multiple dedicated clock routing or multiple clock trees. Unfortunately, the number of clock trees is fixed. They remain limited to a small number. Even if an application requires many clock distributions, such a clock distribution cannot be supported in current field programmable gate arrays. This paper therefore presents a proposal of a more flexible clock distribution method based on wiring channels and switching matrices. The method uses general-purpose programmable wires. In addition, to resolve clock skew increase difficulties, we have introduced a new flip-flop with a two-phase clock signal. This paper presents simulation results obtained using the proposed clock distribution method on an originally designed field programmable gate array. In addition, experimentally obtained results indicate that the proposed clock distribution method can function correctly on a Cyclone V field programmable gate array.