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ID 34098
フルテキストURL
著者
Funabiki, Nobuo Okayama University Kaken ID publons researchmap
Singh, Amit University of California
Mukherjee, Arindam University of California
Sadowska, Malgorzata Marek University of California
抄録

Wave-Steering is a new circuit design methodology to realize high throughput circuits by embedding layout friendly structures in silicon. Latches guarantee correct signal arrival times at the input of synthesized modules and maintain the high throughput of operation. This paper presents a global routing technique for networks of wave-steered blocks. Latches can be distributed along interconnects. Their number depends on net topologies and signal ordering at the inputs of wave steered blocks. here, we route nets using Steiner tree heuristics and determine signal ordering and latch positions on interconnect. The problem of total latch number minimization is solved using SAT formulation. Experimental results on benchmark circuits show the efficiency of our technique. We achieve on average a 40% latch reduction at minimum latency over un-optimized circuits operating at 250 MHz in 0.25 μm CMOS technology

キーワード
binary decision diagrams
circuit layout CAD
flip-flops
integrated circuit layout
network routing
備考
Digital Object Identifier: 10.1109/DSD.2001.952358
Published with permission from the copyright holder. This is the institute's copy, as published in Digital Systems, Design, 2001. Proceedings. Euromicro Symposium on, 4-6 September 2001, Pages 430-436.
Publisher URL:http://dx.doi.org/10.1109/DSD.2001.952358
Copyright © 2001 IEEE. All rights reserved.
発行日
2001-9
出版物タイトル
Digital Systems
開始ページ
430
終了ページ
436
資料タイプ
学術雑誌論文
言語
English
査読
有り
DOI
Submission Path
electrical_engineering/71